8e79f2ee9c
Based on Nekogram. Key additions: - Rebrand to FoxiGram (app name, APK name, applicationId com.foxigram.app) - Embedded Xray (VLESS+Reality) proxy client via JNI libxray.so - Bundled hidden one-tap proxies (LTE + WiFi), read-only in UI - Auto-restore proxy on restart, rebind to active network (LTE/WiFi) - Server credentials externalized to git-ignored XrayServers.java (+ template) - libxray Go source included; compiled .so, keystore, google-services.json ignored
281 lines
10 KiB
C++
281 lines
10 KiB
C++
// Copyright 1995-2016 The OpenSSL Project Authors. All Rights Reserved.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <openssl/base.h>
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#if !defined(OPENSSL_NO_ASM) && \
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(defined(OPENSSL_X86) || defined(OPENSSL_X86_64))
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#include <inttypes.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#if defined(_MSC_VER)
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#include <immintrin.h>
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#include <intrin.h>
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#endif
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#include "internal.h"
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// OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX
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// is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through
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// |*out_edx|.
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static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx,
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uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) {
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#if defined(_MSC_VER)
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int tmp[4];
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__cpuid(tmp, (int)leaf);
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*out_eax = (uint32_t)tmp[0];
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*out_ebx = (uint32_t)tmp[1];
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*out_ecx = (uint32_t)tmp[2];
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*out_edx = (uint32_t)tmp[3];
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#elif defined(__pic__) && defined(OPENSSL_32_BIT)
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// Inline assembly may not clobber the PIC register. For 32-bit, this is EBX.
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// See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602.
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__asm__ volatile(
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"xor %%ecx, %%ecx\n"
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"mov %%ebx, %%edi\n"
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"cpuid\n"
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"xchg %%edi, %%ebx\n"
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: "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
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: "a"(leaf));
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#else
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__asm__ volatile(
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"xor %%ecx, %%ecx\n"
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"cpuid\n"
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: "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
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: "a"(leaf));
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#endif
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}
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// OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR).
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// Currently only XCR0 is defined by Intel so |xcr| should always be zero.
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static uint64_t OPENSSL_xgetbv(uint32_t xcr) {
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#if defined(_MSC_VER)
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return (uint64_t)_xgetbv(xcr);
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#else
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uint32_t eax, edx;
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__asm__ volatile("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
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return (((uint64_t)edx) << 32) | eax;
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#endif
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}
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static bool os_supports_avx512(uint64_t xcr0) {
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#if defined(__APPLE__)
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// The Darwin kernel had a bug where it could corrupt the opmask registers.
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// See
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// https://community.intel.com/t5/Software-Tuning-Performance/MacOS-Darwin-kernel-bug-clobbers-AVX-512-opmask-register-state/m-p/1327259
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// Darwin also does not initially set the XCR0 bits for AVX512, but they are
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// set if the thread tries to use AVX512 anyway. Thus, to safely and
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// consistently use AVX512 on macOS we'd need to check the kernel version as
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// well as detect AVX512 support using a macOS-specific method. We don't
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// bother with this, especially given Apple's transition to arm64.
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return false;
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#else
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return (xcr0 & 0xe6) == 0xe6;
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#endif
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}
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// handle_cpu_env applies the value from |in| to the CPUID values in |out[0]|
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// and |out[1]|. See the comment in |OPENSSL_cpuid_setup| about this.
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static void handle_cpu_env(uint32_t *out, const char *in) {
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const int invert_op = in[0] == '~';
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const int or_op = in[0] == '|';
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const int skip_first_byte = invert_op || or_op;
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const int hex = in[skip_first_byte] == '0' && in[skip_first_byte + 1] == 'x';
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int sscanf_result;
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uint64_t v;
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if (hex) {
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sscanf_result = sscanf(in + invert_op + 2, "%" PRIx64, &v);
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} else {
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sscanf_result = sscanf(in + invert_op, "%" PRIu64, &v);
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}
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if (!sscanf_result) {
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return;
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}
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if (invert_op) {
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out[0] &= ~v;
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out[1] &= ~(v >> 32);
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} else if (or_op) {
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out[0] |= v;
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out[1] |= (v >> 32);
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} else {
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out[0] = v;
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out[1] = v >> 32;
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}
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}
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void OPENSSL_cpuid_setup(void) {
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// Determine the vendor and maximum input value.
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uint32_t eax, ebx, ecx, edx;
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0);
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uint32_t num_ids = eax;
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int is_intel = ebx == 0x756e6547 /* Genu */ && //
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edx == 0x49656e69 /* ineI */ && //
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ecx == 0x6c65746e /* ntel */;
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int is_amd = ebx == 0x68747541 /* Auth */ && //
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edx == 0x69746e65 /* enti */ && //
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ecx == 0x444d4163 /* cAMD */;
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uint32_t extended_features[2] = {0};
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if (num_ids >= 7) {
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7);
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extended_features[0] = ebx;
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extended_features[1] = ecx;
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}
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OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1);
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const uint32_t base_family = (eax >> 8) & 15;
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const uint32_t base_model = (eax >> 4) & 15;
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uint32_t family = base_family;
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uint32_t model = base_model;
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if (base_family == 15) {
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const uint32_t ext_family = (eax >> 20) & 255;
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family += ext_family;
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}
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if (base_family == 6 || base_family == 15) {
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const uint32_t ext_model = (eax >> 16) & 15;
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model |= ext_model << 4;
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}
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if (is_amd) {
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if (family < 0x17 || (family == 0x17 && 0x70 <= model && model <= 0x7f)) {
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// Disable RDRAND on AMD families before 0x17 (Zen) due to reported
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// failures after suspend.
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// https://bugzilla.redhat.com/show_bug.cgi?id=1150286
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// Also disable for family 0x17, models 0x70–0x7f, due to possible RDRAND
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// failures there too.
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ecx &= ~(1u << 30);
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}
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}
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// Reserved bit #30 is repurposed to signal an Intel CPU.
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if (is_intel) {
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edx |= (1u << 30);
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} else {
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edx &= ~(1u << 30);
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}
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uint64_t xcr0 = 0;
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if (ecx & (1u << 27)) {
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// XCR0 may only be queried if the OSXSAVE bit is set.
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xcr0 = OPENSSL_xgetbv(0);
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}
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// See Intel manual, volume 1, section 14.3.
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if ((xcr0 & 6) != 6) {
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// YMM registers cannot be used.
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ecx &= ~(1u << 28); // AVX
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ecx &= ~(1u << 12); // FMA
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ecx &= ~(1u << 11); // AMD XOP
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extended_features[0] &= ~(1u << 5); // AVX2
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extended_features[1] &= ~(1u << 9); // VAES
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extended_features[1] &= ~(1u << 10); // VPCLMULQDQ
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}
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// See Intel manual, volume 1, sections 15.2 ("Detection of AVX-512 Foundation
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// Instructions") through 15.4 ("Detection of Intel AVX-512 Instruction Groups
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// Operating at 256 and 128-bit Vector Lengths").
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if (!os_supports_avx512(xcr0)) {
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// Without XCR0.111xx11x, no AVX512 feature can be used. This includes ZMM
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// registers, masking, SIMD registers 16-31 (even if accessed as YMM or
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// XMM), and EVEX-coded instructions (even on YMM or XMM). Even if only
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// XCR0.ZMM_Hi256 is missing, it isn't valid to use AVX512 features on
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// shorter vectors, since AVX512 ties everything to the availability of
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// 512-bit vectors. See the above-mentioned sections of the Intel manual,
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// which say that *all* these XCR0 bits must be checked even when just using
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// 128-bit or 256-bit vectors, and also volume 2a section 2.7.11 ("#UD
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// Equations for EVEX") which says that all EVEX-coded instructions raise an
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// undefined-instruction exception if any of these XCR0 bits is zero.
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extended_features[0] &= ~(1u << 16); // AVX512F
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extended_features[0] &= ~(1u << 17); // AVX512DQ
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extended_features[0] &= ~(1u << 21); // AVX512IFMA
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extended_features[0] &= ~(1u << 26); // AVX512PF
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extended_features[0] &= ~(1u << 27); // AVX512ER
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extended_features[0] &= ~(1u << 28); // AVX512CD
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extended_features[0] &= ~(1u << 30); // AVX512BW
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extended_features[0] &= ~(1u << 31); // AVX512VL
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extended_features[1] &= ~(1u << 1); // AVX512VBMI
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extended_features[1] &= ~(1u << 6); // AVX512VBMI2
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extended_features[1] &= ~(1u << 11); // AVX512VNNI
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extended_features[1] &= ~(1u << 12); // AVX512BITALG
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extended_features[1] &= ~(1u << 14); // AVX512VPOPCNTDQ
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}
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// Repurpose the bit for the removed MPX feature to indicate when using zmm
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// registers should be avoided even when they are supported. (When set, AVX512
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// features can still be used, but only using ymm or xmm registers.) Skylake
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// suffered from severe downclocking when zmm registers were used, which
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// affected unrelated code running on the system, making zmm registers not too
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// useful outside of benchmarks. The situation improved significantly by Ice
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// Lake, but a small amount of downclocking remained. (See
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// https://lore.kernel.org/linux-crypto/e8ce1146-3952-6977-1d0e-a22758e58914@intel.com/)
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// We take a conservative approach of not allowing zmm registers until after
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// Ice Lake and Tiger Lake, i.e. until Sapphire Rapids on the server side.
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//
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// AMD CPUs, which support AVX512 starting with Zen 4, have not been reported
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// to have any downclocking problem when zmm registers are used.
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if (is_intel && family == 6 &&
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(model == 85 || // Skylake, Cascade Lake, Cooper Lake (server)
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model == 106 || // Ice Lake (server)
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model == 108 || // Ice Lake (micro server)
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model == 125 || // Ice Lake (client)
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model == 126 || // Ice Lake (mobile)
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model == 140 || // Tiger Lake (mobile)
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model == 141)) { // Tiger Lake (client)
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extended_features[0] |= 1u << 14;
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} else {
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extended_features[0] &= ~(1u << 14);
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}
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OPENSSL_ia32cap_P[0] = edx;
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OPENSSL_ia32cap_P[1] = ecx;
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OPENSSL_ia32cap_P[2] = extended_features[0];
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OPENSSL_ia32cap_P[3] = extended_features[1];
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const char *env1, *env2;
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env1 = getenv("OPENSSL_ia32cap");
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if (env1 == NULL) {
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return;
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}
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// OPENSSL_ia32cap can contain zero, one or two values, separated with a ':'.
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// Each value is a 64-bit, unsigned value which may start with "0x" to
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// indicate a hex value. Prior to the 64-bit value, a '~' or '|' may be given.
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//
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// If the '~' prefix is present:
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// the value is inverted and ANDed with the probed CPUID result
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// If the '|' prefix is present:
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// the value is ORed with the probed CPUID result
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// Otherwise:
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// the value is taken as the result of the CPUID
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//
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// The first value determines OPENSSL_ia32cap_P[0] and [1]. The second [2]
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// and [3].
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handle_cpu_env(&OPENSSL_ia32cap_P[0], env1);
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env2 = strchr(env1, ':');
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if (env2 != NULL) {
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handle_cpu_env(&OPENSSL_ia32cap_P[2], env2 + 1);
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}
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}
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#endif // !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64)
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