8e79f2ee9c
Based on Nekogram. Key additions: - Rebrand to FoxiGram (app name, APK name, applicationId com.foxigram.app) - Embedded Xray (VLESS+Reality) proxy client via JNI libxray.so - Bundled hidden one-tap proxies (LTE + WiFi), read-only in UI - Auto-restore proxy on restart, rebind to active network (LTE/WiFi) - Server credentials externalized to git-ignored XrayServers.java (+ template) - libxray Go source included; compiled .so, keystore, google-services.json ignored
214 lines
7 KiB
C
214 lines
7 KiB
C
// Copyright 2018 The BoringSSL Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// https://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef OPENSSL_HEADER_CRYPTO_FIPSMODULE_SHA_INTERNAL_H
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#define OPENSSL_HEADER_CRYPTO_FIPSMODULE_SHA_INTERNAL_H
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#include <openssl/base.h>
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#include "../../internal.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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// Define SHA{n}[_{variant}]_ASM if sha{n}_block_data_order[_{variant}] is
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// defined in assembly.
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#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM)
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#define SHA1_ASM_NOHW
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#define SHA256_ASM_NOHW
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#define SHA512_ASM_NOHW
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#define SHA1_ASM_HW
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inline int sha1_hw_capable(void) { return CRYPTO_is_ARMv8_SHA1_capable(); }
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#define SHA1_ASM_NEON
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void sha1_block_data_order_neon(uint32_t state[5], const uint8_t *data,
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size_t num);
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#define SHA256_ASM_HW
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inline int sha256_hw_capable(void) { return CRYPTO_is_ARMv8_SHA256_capable(); }
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#define SHA256_ASM_NEON
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void sha256_block_data_order_neon(uint32_t state[8], const uint8_t *data,
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size_t num);
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// Armv8.2 SHA-512 instructions are not available in 32-bit.
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#define SHA512_ASM_NEON
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void sha512_block_data_order_neon(uint64_t state[8], const uint8_t *data,
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size_t num);
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#elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_AARCH64)
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#define SHA1_ASM_NOHW
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#define SHA256_ASM_NOHW
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#define SHA512_ASM_NOHW
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#define SHA1_ASM_HW
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inline int sha1_hw_capable(void) { return CRYPTO_is_ARMv8_SHA1_capable(); }
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#define SHA256_ASM_HW
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inline int sha256_hw_capable(void) { return CRYPTO_is_ARMv8_SHA256_capable(); }
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#define SHA512_ASM_HW
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inline int sha512_hw_capable(void) { return CRYPTO_is_ARMv8_SHA512_capable(); }
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#elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86)
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#define SHA1_ASM_NOHW
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#define SHA256_ASM_NOHW
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#define SHA512_ASM_NOHW
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#define SHA1_ASM_SSSE3
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inline int sha1_ssse3_capable(void) {
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return CRYPTO_is_SSSE3_capable();
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}
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void sha1_block_data_order_ssse3(uint32_t state[5], const uint8_t *data,
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size_t num);
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#define SHA1_ASM_AVX
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inline int sha1_avx_capable(void) {
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// AMD CPUs have slow SHLD/SHRD. See also the discussion in sha1-586.pl.
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//
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// TODO(crbug.com/42290564): Should we enable SHAEXT on 32-bit x86?
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return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
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}
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void sha1_block_data_order_avx(uint32_t state[5], const uint8_t *data,
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size_t num);
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#define SHA256_ASM_SSSE3
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inline int sha256_ssse3_capable(void) {
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return CRYPTO_is_SSSE3_capable();
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}
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void sha256_block_data_order_ssse3(uint32_t state[8], const uint8_t *data,
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size_t num);
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#define SHA256_ASM_AVX
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inline int sha256_avx_capable(void) {
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// AMD CPUs have slow SHLD/SHRD. See also the discussion in sha1-586.pl.
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//
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// TODO(crbug.com/42290564): Should we enable SHAEXT on 32-bit x86?
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return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
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}
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void sha256_block_data_order_avx(uint32_t state[8], const uint8_t *data,
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size_t num);
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#define SHA512_ASM_SSSE3
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inline int sha512_ssse3_capable(void) {
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return CRYPTO_is_SSSE3_capable();
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}
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void sha512_block_data_order_ssse3(uint64_t state[8], const uint8_t *data,
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size_t num);
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#elif !defined(OPENSSL_NO_ASM) && defined(OPENSSL_X86_64)
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#define SHA1_ASM_NOHW
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#define SHA256_ASM_NOHW
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#define SHA512_ASM_NOHW
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#define SHA1_ASM_HW
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inline int sha1_hw_capable(void) {
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return CRYPTO_is_x86_SHA_capable() && CRYPTO_is_SSSE3_capable();
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}
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#define SHA1_ASM_AVX2
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inline int sha1_avx2_capable(void) {
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return CRYPTO_is_AVX2_capable() && CRYPTO_is_BMI2_capable() &&
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CRYPTO_is_BMI1_capable();
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}
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void sha1_block_data_order_avx2(uint32_t state[5], const uint8_t *data,
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size_t num);
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#define SHA1_ASM_AVX
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inline int sha1_avx_capable(void) {
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// AMD CPUs have slow SHLD/SHRD. See also the discussion in sha1-586.pl. Zen
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// added the SHA extension, so this is moot on newer AMD CPUs.
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return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
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}
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void sha1_block_data_order_avx(uint32_t state[5], const uint8_t *data,
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size_t num);
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#define SHA1_ASM_SSSE3
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inline int sha1_ssse3_capable(void) { return CRYPTO_is_SSSE3_capable(); }
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void sha1_block_data_order_ssse3(uint32_t state[5], const uint8_t *data,
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size_t num);
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#define SHA256_ASM_HW
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inline int sha256_hw_capable(void) {
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// Note that the original assembly did not check SSSE3.
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return CRYPTO_is_x86_SHA_capable() && CRYPTO_is_SSSE3_capable();
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}
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#define SHA256_ASM_AVX
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inline int sha256_avx_capable(void) {
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// AMD CPUs have slow SHLD/SHRD. See also the discussion in sha1-586.pl. Zen
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// added the SHA extension, so this is moot on newer AMD CPUs.
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return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
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}
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void sha256_block_data_order_avx(uint32_t state[8], const uint8_t *data,
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size_t num);
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#define SHA256_ASM_SSSE3
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inline int sha256_ssse3_capable(void) { return CRYPTO_is_SSSE3_capable(); }
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void sha256_block_data_order_ssse3(uint32_t state[8], const uint8_t *data,
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size_t num);
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#define SHA512_ASM_AVX
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inline int sha512_avx_capable(void) {
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// AMD CPUs have slow SHLD/SHRD. See also the discussion in sha1-586.pl.
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//
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// TODO(crbug.com/42290564): Fixing and enabling the AVX2 implementation would
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// mitigate this on newer AMD CPUs.
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return CRYPTO_is_AVX_capable() && CRYPTO_is_intel_cpu();
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}
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void sha512_block_data_order_avx(uint64_t state[8], const uint8_t *data,
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size_t num);
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#endif
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#if defined(SHA1_ASM_HW)
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void sha1_block_data_order_hw(uint32_t state[5], const uint8_t *data,
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size_t num);
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#endif
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#if defined(SHA1_ASM_NOHW)
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void sha1_block_data_order_nohw(uint32_t state[5], const uint8_t *data,
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size_t num);
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#endif
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#if defined(SHA256_ASM_HW)
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void sha256_block_data_order_hw(uint32_t state[8], const uint8_t *data,
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size_t num);
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#endif
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#if defined(SHA256_ASM_NOHW)
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void sha256_block_data_order_nohw(uint32_t state[8], const uint8_t *data,
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size_t num);
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#endif
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#if defined(SHA512_ASM_HW)
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void sha512_block_data_order_hw(uint64_t state[8], const uint8_t *data,
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size_t num);
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#endif
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#if defined(SHA512_ASM_NOHW)
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void sha512_block_data_order_nohw(uint64_t state[8], const uint8_t *data,
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size_t num);
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#endif
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#if defined(__cplusplus)
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} // extern "C"
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#endif
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#endif // OPENSSL_HEADER_CRYPTO_FIPSMODULE_SHA_INTERNAL_H
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